In recent years, the design of integrated circuits has seen annual increases in integration level according to Moore's law, and integrated circuit designs become more complex with each passing day. At present a register transfer level (RTL) design using a hardware description language (HDL), which is the mainstream of integrated circuit design, affords greater design abstraction compared with gate-level design in which circuits are designed using logic gates, and so it is possible to greatly reduce the number of integrated circuit design processes. An HDL description file is logically synthesized and converted into a netlist describing a gate-level circuit, cells registered in a library are allocated to gates in the netlist, and wiring connecting cells and clock supply circuits are laid out, so that design data for an LSI chip is thus generated.
However, since an HDL description with a low degree of abstraction for a circuit has to be developed, RTL designs are steadily becoming unable to accommodate constantly increasing circuit scales, and high-level designs with still higher degrees of abstraction than RTL design are coming into use. As input languages (high-level languages) used in high-level design, software languages are frequently used, and the most frequently used are the C/C++ language, SystemC with a class library for hardware description implemented, and similar. In high-level design, such high-level languages are used to generate behavior description files which describe circuit algorithms or functions.
A behavior description written in a high-level language is converted into an HDL file by a type of compiler called a high-level synthesizer. High-level synthesizers are described in Japanese Patent Application Laid-open No. 2010-165334, Japanese Patent Application Laid-open No. 2000-57180, Japanese Patent Application Laid-open No. 2004-265224 and Japanese Patent Application Laid-open No. H6-325124.